The present invention relates to a processor system in which a synchronous dynamic memory is used in a storage apparatus for storing data or instructions.
In a conventional processor system, the main storage apparatus for storing data or instructions has been constructed by using a cheap, general purpose dynamic memory. An example of a general architecture of the main storage apparatus of a work station using a plurality of dynamic memories can be seen in, for example, L. Johnson et al., "System Level ASIC Design for Hewlett-Packard's Low Cost PA-RISC Workstations", ICCD '91, International Conference on Computer Design, Proceeding, pp. 132-133.
Specifications of such a general purpose dynamic memory are seen in Hitachi IC Memory Handbook 2, "DRAM, DRAM Module" ('91.9), pp. 389-393. As will be seen from the above, the conventional dynamic memory does not have a clock input which serves as an input signal to a chip and during read/write, an internal operation clock was generated in the chip from other control input signals. Furthers a mode register for prescribing the operation mode of the dynamic memory was not provided therein and as a consequence, the operation mode of the conventional dynamic memory was fundamentally a single mode. Moreover, the dynamic memory was constructed of a single internal bank.
On the other hand NIKKEI ELECTRONICS, 1992. 5.11 (No. 553), pp. 143-147 introduces, as a dynamic memory which is accessible at a twice or 4 times higher speed than before, a synchronous dynamic memory having a plurality of banks and a built-in register which can set the operation mode of these banks (such as delay from /RAS transition or /CAS transition, the number of words accessible sequentially (wrap length), and the order of addresses of input/output data pieces which are accessed sequentially).